| Abstract |
The CMOS industry relies on the capabilities of engineers to control atomic positions at sub-nm scale across several interfaces. The formation of abrupt interfaces is heavily dependent on the thermal budget during their formation and of any other subsequent thermal treatments during device fabrication. As device dimensions decrease, the thicknesses of all junctions and interfaces must be reduced so that they do not become the major fractional volume of the whole device. In that framework, ultra fast annealing is becoming a key technology to enable the fabrication of nano scaled devices.
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