A method for fabrication of semiconductor device comprising a first wafer comprising first single crystal layer comprising first transistors, first alignment marks, and first transistors interconnect layers comprising at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum; and comprising a step of implant and high temperature activation to form a conductive layer within a second wafer; and forming a second crystallized layer on top of said first wafer by transferring said conductive layer using ion-cut process, and forming second transistors on said second crystallized layer wherein said second transistors source and drain comprises portion of said first conductive layer.

A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias.

A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks.

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layers; wherein the second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands wherein each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.