The HIDING DIES project aims to develop a highly innovative technology for embedding active chips into high-densityprinted circuit boards. This 3-dimensional integration will enable a high degree of miniaturization, improved electrical andthermal performance for mobile and communication products.The technological steps are bonding of thin chips (50 µm) on multilayer substrates, embedding of the chips by vacuumlamination of a dielectric layer (RCC), followed by laser drilling of via holes to the chip contacts and to the substrate andfinally metallization of vias and conductor lines. For a further increase of functional density integrated passive components can be combined with the chip embedding. The resulting sub-systems with integrated components additionally allow assembly of surface mount devices on the bottom and top surface.All required process steps will be based on existing technologies, however their combination to a cost-effective high-yielding technology require significant scientific and technological research. Besides the process development, a detailedunderstanding of thermo-mechanical, thermal and electrical performance of such integrated systems has to be achieved.Furthermore development effort has to be made to explore technological limits by handling and bonding very large and very thin chips ( 50 µm) and by stacking multiple layers with integrated components.The achievement of the development goals will be assessed using two demonstrators, specified by end users. A sensordevice combines a surface mounted MEMS chip with embedded control circuits, resulting in an extremely small footprint.The other demonstrator is a power RF application. Target is to create a miniaturized module with excellent electrical andheat conducting properties. With the IC's embedded in the substrate, short connections to filter structures and assembled discrete SMD's at the surface, a compact miniature module can be created.

Smart power circuits and technologies contribute in a unique way to the realization of the system-on-chip concept by combining digital logic with analogue signal processing and power and high voltage switching. The main objective of this project is to enable a robust design of smart power circuits leading to a first-time-right design with built-in reliability and thus avoiding very costly over-dimensioning. To achieve this ambitious goal, compact models will be built that accurately describe power device operation including extensions to verify safe-operating area conditions. The devices to be modelled include the lateral DMOS, vertical DMOS and LIGBT fabricated in bulk silicon and power devices realized in advanced SOI technology. Model extensions are planned for device ageing due to hot-carrier injection, statistics due process variations, device matching and layout effects such as large area closed-cell matrices. An important feature will be an accurate description of the internal device temperature plus a coupling to package thermal models and EMC modelling. The final goal is to achieve a system level design flow for smart-power SoC using complex transistor level simulations or generated black-box models. Full smart power circuits will be simulated with the new design flow and models will be assessed and calibrated against experimental measurements. The gain in performance and robustness will be quantified.The project therefore aims at providing the EC 'power' industrial community with new, highly robust tools to design and characterize smart power devices and circuits. This will strengthen and significantly advance ECs position as a fast growing, world supplier of smart power technologies. Design and fabrication of highly reliable and efficient Smart Power circuits is one of the most important strategic ways to reduce drastically energy losses in power systems by ensuring optimal energy conversion at all times.

NANOCMOS is a project integrating in a coherent structure, activities that in the past have been the object of ESPRIT/IST, JESSI/MEDEA projects in the field of CMOS technologies. It focuses on the RTD activities necessary to develop the 45nm, 32nm and below CMOS technologies. From these technology nodes it will be mandatory to introduce revolutionary changes in the materials, process modules, device and metallisation architectures and all related characterization, test, modelling and simulation technologies, to keep the scaling trends viable and make all future IST applications possible. NANOCMOS covers all these aspects. The project include as well important Training and Dissemination activities. A professional Management structure will be implemented. The first objective of the project is the demonstration of feasibility of Front-End and Back-End process modules of the 45nm node CMOS logic technology. The project intents to process as demonstrator a very aggressive SRAM chip displaying worldwide best characteristics. This objective will be achieved within two years from project start. The second objective of the project is to realize exploratory research on critical issues of the materials, devices, interconnect and related characterization and modelling to start preparing the 32/22 nodes considered to be within the limits of the CMOS technologies. The third objective of the project is to prepare the take up of results described in the Objective I and implement a 45nm Full Logic CMOS Process Integration in 300 mm wafers by the end of 2007. This integration will be part of a separate MEDEA+ project. NANOCMOS initial Consortium gathers most of best competences existing in Europe in the domain. It is expected to incorporate new partners, to fulfil already identified tasks. NANOCMOS places Europe on a privileged position in the competition to develop the enabling technologies of the 2010 e-Society.

The approach of the information society has resulted in a tremendous increase in thevolume of wireless communication often giving rise to bottle-necks in the communicationsystems. To alleviate this congestion there is pressure to widen the allocated frequencybands up to millimetre wavelengths and to have terminals that are able to support manystandards. It is understood that conventional components and solutions have limitationsthat will make it difficult to fulfil these requirements. The last five years has seen theemergence of a technology, RF and microwave MicroElectroMechanical Systems (MEMS), thatseeks to overcome these limitations. In this new technology mechanical and electricalfunctions are combined to improve the performance of existing devices, allow on-waferdevice integration and the creation of completely new device systems called Advanced MEMSfor RF and Millimeterwave Communications 'AMICOM' .A consortium has been assembled that believes the merging MEMS technologies with 1Ctechnologies will lead to advanced microsystems that can operate over very broad-bandfrequency ranges. The microsystems will feature innovative functionalities, such ascircuit redundancy, reconfigurability and power management. To realise this microsystemconcept, research and collaboration in many different fields is required including!fabrication technology, materials, electromagnetics, mechanics, thermal and electricalmodelling, characterisation, packaging and reliability.We believe that a Network of Excellence is the most appropriate vehicle with whichto assemble and integrate the isolated competences that exist around Europe in thisfield. In this way a powerful research body will be created that can compete withthe United States and Japan. The idea is to give to the industrial partners accessto a large and transparent body of European competence to help them to enhancetheir competitiveness.

This project is part of a joint European activity which targets at inter-linking the European RandD Centres of Excellence in micro and nanotechnologies to a virtual 300 mm CMOS RandD line. The core partners include industrial 300 mm research sites and pilot lines as well as the major European RandD institutes Fraunhofer, IMEC and LETI. The goal of this project is to enable, on a short term, the co-operation of the European RandD centres by providing a fast and reliable logistic and infrastructure for exchange and transfer mechanism of 300 mm wafers between the RandD sites. Thus, existing 300 mm processing capabilities, newly purchased standard 300 mm equipment and highly innovative alpha or beta site tools finally can be interlinked to a full CMOS RandD line. Furthermore, data about the current status and location of wafers and carriers needs to be tracked, monitored and administrated in a joint database and made securely accessible by all partners via the internet. Demonstrating the feasibility of inter-linking the already existing European RandD Centres of Excellence within the framework of this project should cost-effectively enable in fact the availability of a virtual European 300 mm CMOS RandD line as early as 2005/2006.

Things that think and the communication of people with such things in his environment critically depend oncontactless communication technologies. RF communication devices and protocols have been developed in thepast and exist today, yet in their present form they cannot and will never be used on a large scale to allowcommunication with everyday objects. The fundamental reason for this is the cost of the silicon technologyemployed to realize it. Even in its most optimistic projection, this cost remains at least one order of magnitudehigher than the cost of a technology that has been proven to be truly ubiquitously applicable, such as a barcode.Therefore, a new generation of devices is required to enable ambient intelligence at the right cost point in orderto be truly applicable everywhere and anywhere.The objective of PolyApply is to lay the foundations of a scalable and ubiquitously applicablecommunication technology. The boundary condition is the cost of the microsystem, combining basic RFcommunication with sensor functions. The key to achieving a fundamentally different cost point than what will bereachable in the future with the evolution of the existing technologies (e.g. CMOS), is to resolutely move to adisruptive new manufacturing technology: going from batch processing to in-line manufacturing technology.The semiconductor system envisaged to this end is based on polymers. The scalable aspect refers to the factthat PolyApply does not plan to propose a solution for a certain generation of RF communication devices usefulat one point in time, but rather intends to develop generic technologies with a meaningful impact in the mid- andlong term. In other words, the developed technologies will lead to an extendable family of products, ranging from'simple' RF tags at ultra-low cost to RF communication devices with complex functionality such as integrated re-writable memory, sensory inputs, display, etc...

The electronics manufacturing sector has seen significant changes over the past two years. Volume manufacturing has become a commodity service resulting in: creation of multinational manufacturing service providers; migration of volume operations to low-cost locations external to EC and the evolution of manufacturing technology only ideally suited to high volume production. The future of the industry will be based in an evolving, dynamic SME community. SME manufacturers survive ';by providing low-volume, high variety, mixed-batch manufacture or production of niche and high-value added products. This community faces challenges from market, manufacturing technology and legislative pressures. The pressures of mass-customisation, decreasing life cycles and integration of multifunctional features, such as MST and MEMs technologies, requires the adoption of sophisticated manufacturing capabilities with flexibility to. cope with a broad mix of products and volumes. Manufacturing technology has evolved towards efficiency in volume production, with scant regard to flexibility and rapid changeover for lower volume production. Agility will be a key element to SME survival and future investment. The WEEE directive banning lead requires SMEs to adopt new manufacturing practices, requiring another dimension of flexibility in capability and potential cost impacts from expensive consumables (N2) and higher energy requirements. The lead-free changeover also requires the understanding of these materials in production and product life-cycle. Flex-eman offers a solution to these challenges by utilising individual precision soldering chambers combined in a work-cell serviced by intelligent materials handling and control systems. This replaces an inflexible production process with an agile system, specifically designed jor cost-efficiency in manufacture of mixed product and batch sizes. The system is inherently fault-tolerant, eco-friendly and incorporates state of th

SINANO aims to strengthen European scientific and technological excellence in the field of electronic,Si-based nanodevices for terascale integrated circuits. Over the next quarter century considerablechallenges exist to push the limits of silicon integration down to nanometric dimensions. These can bestbe addressed by integration, at the European level, of the individually excellent research capabilitiesalready existing in the main university and national research centers. SINANO's activities, with long-term and multidisciplinary objectives, could herald a revolution in 1C technology, involving integrationof nanoscale CMOS and emerging post-CMOS logic and memory devices. SINANO will work toenhance device performance and integration, to meet the ever increasing demands of communicationsand computing. The network includes partners with expertise required to develop these advanceddevices, from basic materials science through design and fabrication to characterisation and devicemodelling. This ambitious programme will make Europe the world-leading center for nanoelectronicdevices - from fundamentals through to realisation, advancing this crucial technology to underpin theEuropean economy over the coming decades.The proposed Joint Programme of Activities includes significant integrating activities: coordination ofthe partners' activities leading to the extension of specialisation, a joint technical research programme,sharing Joint Research Platforms for Processing and Characterisation, management of knowledge, staffexchanges, electronic communication (e-mail, conferencing, website), activities to spread excellence(training researchers, students and technical staff, dissemination of results by open EuropeanWorkshops). It will be orchestrated by a unified management structure comprising a Governing Board,Executive and Scientific Committee consisting of WP leaders and representatives of the main industrial partners, and WP leaders.

Secure communication is an essential need for companies, public institutions and in particular the individual citizen. Currently used encryption systems are vulnerable due to the increasing power of computer technology, the emergence of new code-breaking algorithms, and the imperfections of public key infrastructures. Methods considered as acceptably secure today will have a significant risk of becoming weak tomorrow. On the other hand, with quantum cryptography a technology has been developed within the last decade that is provably secure against arbitrary computing power, and even against quantum computer attacks. When becoming operational quantum cryptography will raise communication security on an essentially higher level. The vision of SECOQC is to provide European citizens, companies and institutions with a tool that allows facing the threats of future interception technologies, thus creating significant advantages for European economy. With SECOQC the basis will be laid for a long-range high security communication network that combines the entirely novel technology of quantum key distribution with components of classical computer science and cryptography. Within the project the following goals will be achieved: - Realisation of a fully functional, real-time, ready-to-market Quantum Key Distribution (QKD) point-to-point communication technology; - Development of an abstract level architecture allowing high security long-range communication by integrating the QKD technology and a set of cryptographic protocols; - Design of a real-life, user-oriented network for practical implementation of QKD based long range secure communication. To achieve this goal, all experience and resources available within the European Research Area are to be integrated and combined with the expertise of developers and companies within the fields of network integration, cryptography, electronics, security, and software development.

The EUROSOI network embraces a broad range of research areas related to Silicon-On-lnsulator technology(from materials to end-user electronic applications in traditionally strong European industrial sectors such asautomotive, communications, space). EUROSOI aims at federating the existing research work on SOI topics andat providing an appropriate communication channel between academic groups and industrial production centres.EUROSOI coordination efforts will be focused on fostering different activities to improve the lack of industrialdevelopment in Europe in SOI topics. A network of research centres, industries and end-users is the appropriatetool to structure and organize the existing RandD work on SOI topics, and achieve a critical mass to efficientlyclose the gap between academic groups and industry, which is responsible for the weakness of EuropeanIndustry with regard to SOI. Key actions to reach the above-mentioned objectives are: i)to promote interactionbetween scientists, ii)to take advantage of the previous experience of research groups, iii)to join forces tomaximize the synergy between individual skills, thus obtaining the best achievable global results, and iv) toprovide an appropriate communication channel between academic groups and industrial production centres.EUROSOI will contribute to this by: a)The exchange of information during the workshops organized by thenetwork. (b)Scientific exchange between partners by research visits of scientist and student grants, (c) A web-based database on work by SOI containing: news, resources, project results, reports, links, seminars, training,courses, job opportunities, grants, (d) Elaboration of the European SOI Roadmap: identification of scientificpriority areas and formulation of research and development strategies, (e) Elaboration of Who is Who Guide inSOI.