This project aims to encourage and facilitate the participation of Small and Medium Sized (SMEs) companies

from the candidate countries in FP6, in particular in the nanotecnologies and nanomaterial fields, through the

provision of in-depth technological intelligence and innovation assistance services.

In order to accomplish this mission, the project partners, which come from nine EU and candidate countries (CZ,

DE, ES, FR, HU, LU, PL, RO, SK), will support SMEs with the following actions:

• Raise awareness on EU funding opportunities and promote R&D cooperation.

• Gather information on relevant Integrated Projects (IP) and Networks of Excellence (NoE) already being

developed, as well as on FP5 project results. Provide assistance and intermediation services to the

coordinators of these Integrated projects (IP) and Networks of excellence (NoE) in order to promote the

incorporation of additional SMEs as technology providers or end users. In total, 60 companies are

expected to be incorporated in ongoing projects of IP and NoE, and follow up activities of the selected

successful 5th FP RTD projects, facilitating the creation of new groupings with the existent partners.

• Perform 100 company technology audits in order to identify needs, current capabilities, best practices

and future developments needs.

• Support SMEs to put eligible and successful proposals together. Support the submission of 22 EC RTD

proposals, amongst cooperative research projects (CRAFT), collective research projects and specific

targeted research projects (STREP).

• Provide 200 SMEs with technological intelligence services in the nanotechnology and nanomaterial

fields.

• Dissemination to 500 SMEs of good practices and of innovative research results to sectors of potential

application. The sectors where the NANOMAT project will concentrate are the automotive, electronics

and health sectors.

• Tailor-made training to 300 SMEs in economic and te

Much world-wide effort is being devoted to research into nanoelectronic and nanophotonics devices, but less effort is being applied to examining system architectures, which might use these devices to best advantage. Such research is needed, so that present-day increases in computing power can be extended into the future. To achieve such increases will be a major technological challenge, and proactive research and planning is needed now. Some unanswered technical questions are: Can devices be assembled into ultra-high density circuits? Are any of these devices fundamentally unsuitable? Will factors such as size variations affect performance? Can manufacturing faults and transient errors be overcome using fault tolerance? Will the circuits have better performance than CMOS-type circuits? Will nanoscale circuits be cheaper than CMOS? Besides these technical questions, two other questions must also be asked: What systems research is being carried out now, and what gaps are there? - and are there enough trained people in Europe who are capable of solving these problems? Some but not all of these questions are being looked at under existing EC initiatives. We therefore propose a survey which, starting from the existing EC Nanoelectronics Roadmap, would report on existing European expertise in the following areas: 1. existing and proposed nanoelectronic/photonic devices 2. small circuits: theory and practice 3. ultralarge circuits: theory and practice 4. conventional architectural concepts 5. unconventional concepts 6. new concepts 7. known problems 8. 'system on a chip' and 3D systems 9. applications: performance requirements 10. availability and training of human resources The report will suggest topics where further effort might be applied, ranging from basic theoretical research, through device/circuit fabrication techniques, to possible training and research workshops. Information will also be provided on US and Pacific Rim activity.

Two-dimensional photonic crystals (PhCs) in waveguide geometry are a recent concept for light propagation control, which has seen its main promises verified in the optical range. They have the potential to be the building block of a novel generation of optical circuits combining high-speed processing and very high scale integration. However, for the control of light emission, these 2D PhC suffer from a lack of confinement in the third (vertical) dimension. In this context, three-dimensional issue of nanostructuring, thanks to their bottom-up approach. The purpose of the present experimental and theoretical proposal is to benefit from the versatility and manufacturability of silicon to realize hybrid architectures combining 2D planar PhCs and self-assembled 3D PhCs. The goal is to provide conceptual tools to design advanced photonics architectures combining integrated light sources and routing functions for telecommunications wavelenghts. The basic issues addressed will be spontaneous emission control in 3D PhCs, routing functions in 2D PhCs, electrical addressing of PhCs, and coupling between 2D and 3D PhC in hybrid architectures. The present project will address many of the main targets of the thematic priority In-formation Society Technologies, such as the access to all part of the society to the information, by mean of user-friendly and secured services.

SINANO aims to strengthen European scientific and technological excellence in the field of electronic,Si-based nanodevices for terascale integrated circuits. Over the next quarter century considerablechallenges exist to push the limits of silicon integration down to nanometric dimensions. These can bestbe addressed by integration, at the European level, of the individually excellent research capabilitiesalready existing in the main university and national research centers. SINANO's activities, with long-term and multidisciplinary objectives, could herald a revolution in 1C technology, involving integrationof nanoscale CMOS and emerging post-CMOS logic and memory devices. SINANO will work toenhance device performance and integration, to meet the ever increasing demands of communicationsand computing. The network includes partners with expertise required to develop these advanceddevices, from basic materials science through design and fabrication to characterisation and devicemodelling. This ambitious programme will make Europe the world-leading center for nanoelectronicdevices - from fundamentals through to realisation, advancing this crucial technology to underpin theEuropean economy over the coming decades.The proposed Joint Programme of Activities includes significant integrating activities: coordination ofthe partners' activities leading to the extension of specialisation, a joint technical research programme,sharing Joint Research Platforms for Processing and Characterisation, management of knowledge, staffexchanges, electronic communication (e-mail, conferencing, website), activities to spread excellence(training researchers, students and technical staff, dissemination of results by open EuropeanWorkshops). It will be orchestrated by a unified management structure comprising a Governing Board,Executive and Scientific Committee consisting of WP leaders and representatives of the main industrial partners, and WP leaders.

The Microsystems platform for MObile Services and Applications (MiMOSA) is an integrated project done by a strong and synergetic consortium. MiMOSA creates a new open system platform for context-aware mobile services and applications. The approach is mobile phone based, providing the users with a smooth transition from current mobile services to ambient intelligence services. In the area of short-range connectivity, MiMOSA positions itself to low-cost, low-bit rate territory that can be set up with relatively modest investments in the infrastructure. The main focus of MiMOSA is the development of novel low-power microsystems, in particular wireless sensors exploiting the RFID technology, highly integrated readers/writers for RFID tags and sensors, low-power MEMS-based RF components and modules, low-power short-range radios, advanced integration technology, and novel MEMS sensors for context sensitivity and intuitive, user-friendly interfaces. MiMOSA extends the area of telecommunication business to ambient intelligence. The MiMOSA project is organized in 6 work packages including management. Its design approach is strongly human-centred. End users and application developers participate in designing and evaluating how ambient intelligence and short-range communication with environment could be best utilised in the everyday life. User feedback guides the design of the core components of ambient intelligence. To demonstrate the generic characteristics of the platform, MIMOSA develops specific applications with particular emphasis on physical browsing, health monitoring, intelligent housing, fitness/sports, context awareness for ambient intelligence and intuitive user interfaces. The defined approach and results will be disseminated and will lead to innovation in other application domains.Tomorrow's ambient intelligence will be enabled by generic technologies such as proposed by the MiMOSA vision in which cultural, ethical and/or gender issues are directly addressed.

This project is part of a joint European activity which targets at inter-linking the European RandD Centres of Excellence in micro and nanotechnologies to a virtual 300 mm CMOS RandD line. The core partners include industrial 300 mm research sites and pilot lines as well as the major European RandD institutes Fraunhofer, IMEC and LETI. The goal of this project is to enable, on a short term, the co-operation of the European RandD centres by providing a fast and reliable logistic and infrastructure for exchange and transfer mechanism of 300 mm wafers between the RandD sites. Thus, existing 300 mm processing capabilities, newly purchased standard 300 mm equipment and highly innovative alpha or beta site tools finally can be interlinked to a full CMOS RandD line. Furthermore, data about the current status and location of wafers and carriers needs to be tracked, monitored and administrated in a joint database and made securely accessible by all partners via the internet. Demonstrating the feasibility of inter-linking the already existing European RandD Centres of Excellence within the framework of this project should cost-effectively enable in fact the availability of a virtual European 300 mm CMOS RandD line as early as 2005/2006.

The HIDING DIES project aims to develop a highly innovative technology for embedding active chips into high-densityprinted circuit boards. This 3-dimensional integration will enable a high degree of miniaturization, improved electrical andthermal performance for mobile and communication products.The technological steps are bonding of thin chips (50 µm) on multilayer substrates, embedding of the chips by vacuumlamination of a dielectric layer (RCC), followed by laser drilling of via holes to the chip contacts and to the substrate andfinally metallization of vias and conductor lines. For a further increase of functional density integrated passive components can be combined with the chip embedding. The resulting sub-systems with integrated components additionally allow assembly of surface mount devices on the bottom and top surface.All required process steps will be based on existing technologies, however their combination to a cost-effective high-yielding technology require significant scientific and technological research. Besides the process development, a detailedunderstanding of thermo-mechanical, thermal and electrical performance of such integrated systems has to be achieved.Furthermore development effort has to be made to explore technological limits by handling and bonding very large and very thin chips ( 50 µm) and by stacking multiple layers with integrated components.The achievement of the development goals will be assessed using two demonstrators, specified by end users. A sensordevice combines a surface mounted MEMS chip with embedded control circuits, resulting in an extremely small footprint.The other demonstrator is a power RF application. Target is to create a miniaturized module with excellent electrical andheat conducting properties. With the IC's embedded in the substrate, short connections to filter structures and assembled discrete SMD's at the surface, a compact miniature module can be created.

Mechanical resonance is widely applied in high-precision oscillators for a multitude of time-keeping and frequency reference applications. In all such cases, the high-precision resonatingelement consists of an off-chip passive component, such as a quartz crystal. Major drawbackof these off-chip resonator technologies is that they are bulky and must interface withtransistor chips at the boards, posing a bottleneck against the ultimate miniaturization of e.g.wireless devices. The extraordinary small size and high level of integration that can beachieved with silicon MEMS resonators appear to open exceptional possibilities for creatingminiature-scale precision oscillators to be used in e.g. mobile communication and navigationdevices. The aim of the NanoTIMER project is to develop an oscillator with high-accuracyincorporating a silicon MEMS resonator generating frequencies in the 10 to 1500 MHz range.Within the NanoTIMER project, MEMS based oscillators will be realized according to concretespecifications derived from existing applications. The MEMS oscillator will be encapsulatedusing a wafer-level vacuum package technology that is compatible to the oscillatormanufacturing flow. An important feature of the proposed resonator manufacturing process isthe realization of nanometre size (100 nm) transduction gaps, which is of prime importancefor the realization of MEMS resonators functioning in the GHz range. Reliability and drift ofassembled oscillators and its constituent components (resonator and package) will beassessed.The NanoTIMER initiative is a first step towards the realization of 'vibrating' nano-electro-mechanical processors that, combined with traditional CMOS, could open new alternatives forsignal processing in VLSI.

Miniaturizing optical connections and controlling optical processes at the subwavelength scale are expected keytechnologies not only for the future of data processing but also for the development of various sensors needed innanotechnologies. Among other strategies, a promising perspective shows up from the research works on opticalnanodevices involving surface plasmon polaritons sustained by nanostructures, also called plasmonics. Duringthe last years, European laboratories succeeded to build a significant advance over concurrent groups of othercontinents. To ensure the definitive European leadership in this field of research whith a high potential ofindustrial applications, it is now essential to federate the human and technical resources spread in Europe into aNetwork of Excellence aimed at developing prototypes of surface plasmon nanodevices for controlling opticalprocesses at the subwavelength scale. In the framework of well identified scientific and technical objectives, theparticipating organizations propose as aim of the present network of excellence to test an alternative structure ofthe management, evaluation and decision making mechanisms of research projects in order to improve theincisive and target oriented character of the research program.

Silicon CMOS is rapidly running out of steam and the entire semiconductor industry is puzzled about what comes next as the roadmap advances towards the terahertz region. It is clear that virtually every material (gate, gate oxide and channel) used in the current transistor must be replaced within the next 3 - 4 years, without interruption in the industry's pace. Two high mobility material classes are emerging as potential silicon replacement: germanium (Ge) and compound semiconductors (CS). The goal of this project is to find out which one presents the best future technology platform. This formidable question requires a major rethinking of all materials and processes. It will be addressed here from all relevant aspects: advanced large area wafers, novel gate stacks and transistor processing. With a strict focus on a simple and well defined process-flow as well as an innovative, fast materials characterization track, the main strengths and show-stoppers for each material system will be identified.The first objective is to demonstrate that high mobility large area compliant substrates of Ge-on-insulator (GOI) and CS- on-insulator (CSOI) can be obtained. GOI, and CSOI will be grown by developing a 'strained oxide template on Si' technology based on molecular beam epitaxy (MBE). The second objective is to demonstrate high quality gate stacks on Ge and CS. The challenge is to find suitable high-k compounds that can be used as gate dielectrics while maintaining high channel mobilities. The development of amorphous or epitaxial (for double gate) metal gates are also an essential project component.The third objective is to integrate the new channel and gate materials with a 200 mm semiconductor wafer processing line to demonstrate high mobility transistors for a few well chosen material systems.